十字路口交通控制系统设计

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利用VHDL及Quartus进行十字路口交通控制系统设计

一、目标

利用VHDL及Quartus设计一个十字路口交通控制系统，其东西，南北两个方向除了有红、黄、绿灯指示是否允许通行外，还设有时钟，以倒计时方式显示每一路允许通行的时间，绿灯，黄灯，红灯的持续时间分别 40、5和45秒。当东西或南北两路中任一道上出现特殊情况，例如有消防车，警车要去执行任务，此时交通控制系统应可由交警手动控制立即进入特殊运行状态，即两条道上的所有车辆皆停止通行，红灯全亮，时钟停止计时，且其数字在闪烁。当特殊运行状态结束后，管理系统恢复原来的状态，继续正常运行。

二、实现方案

本方案主要由时钟信号产生器，信号灯控制器、分别控制两条通路的两个倒计时控制显示器组成。时钟信号发生器由实验板上的 1Hz 时钟信号源实现。

信号灯控制器模块由分为五种状态的状态机进行实现：
S0:A方向绿灯亮，B方向红灯亮，持续40秒；
S1:A方向黄灯亮，B方向红灯亮，持续5秒；
S2:A方向红灯亮，B方向绿灯亮，持续40秒；
S3:A方向红灯亮，B方向黄灯亮，持续5秒；
S4:紧急状态，A、B方向均红灯亮。
在非紧急状态下，状态机按照S0、S1、S2、S3、S0的顺序进行。
循环。

在紧急状态信号传入时，模块对进入紧急状态前的数字进行存储，同时状态机转入S4。在从紧急状态转入非紧急状态时，读取之前存储的数字，状态机重新进入非紧急状态下的循环。倒计时控制显示器中除正常存储变量Usual外，还引入了Mark，用来标记模块在紧急和非紧急状态间切换的状态，便于在紧急状态下
对倒计时显示器进行闪烁处理。

三、核心代码

1、信号灯控制器

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library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
entity TrafficLight is
  port(
       clk:in std_logic;                  
       emergent:in std_logic;   
       R1,R2:out std_logic;   
       Y1,Y2:out std_logic;      
       G1,G2:out std_logic; 
  );
end TrafficLight;
architecture one of TrafficLight is
	type state is(s0,s1,s2,s3,s4);  
	signal state_now:state:=s0;
	signal count:integer:=0;  
begin
	counter:process(clk)begin
	if(clk'event and clk='1')then
		if(emergent='1')then         
			if(count<90)then
				count<=count+1;
			else
				count<=1;
			end if;
		end if;
	end if;
	end process;
	
	state_trans:process(count)begin
	if(clk'event and clk='1')then
		case state_now is
		when s0=>        
			if(emergent='1')then
				if(count>39)then
					state_now<=s1;
				end if;
			else
				state_now<=s4;
			end if;
		when s1=>     
			if(emergent='1')then
				if(count>44)then
					state_now<=s2;
				end if;
			else
				state_now<=s4;
			end if;
		when s2=>       
			if(emergent='1')then
				if(count>84)then
					state_now<=s3;
				end if;
			else
				state_now<=s4;
			end if;
		when s3=>       
			if(emergent='1')then
				if(count>89)then
					state_now<=s0;
				end if;
			else
				state_now<=s4;
			end if;
		when s4=>       
			if(emergent='1')then
				if(count<39)then
					state_now<=s0;
				elsif(count<44)then
					state_now<=s1;
				elsif(count<84)then
					state_now<=s2;
				elsif(count<89)then
					state_now<=s3;
				end if;
			else
				state_now<=s4;
			end if;
		end case;
		end if;
	end process;
	
	output:process(clk)begin
		case state_now is       
		when s0=>
			R1<='0';		R2<='1';
			G1<='1';		G2<='0';
			Y1<='0';		Y2<='0';
		when s1=>
			R1<='0';		R2<='1';
			G1<='0';		G2<='0';
			Y1<='1';		Y2<='0';
		when s2=>
			R1<='1';		R2<='0';
			G1<='0';		G2<='1';
			Y1<='0';		Y2<='0';
		when s3=>
			R1<='1';		R2<='0';
			G1<='0';		G2<='0';
			Y1<='0';		Y2<='1';
		when s4=>
			R1<='1';		R2<='1';
			G1<='0';		G2<='0';
			Y1<='0';		Y2<='0';
		end case;
	end process;
end one;

2、倒计时显示器模块1

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library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
entity m45 is
  port(
       clk:in std_logic;                          
       emergent:in std_logic;                    
       Output1,Output2:out std_logic_vector(3 downto 0)  
  );
end m45;

architecture one of m45 is
	signal Twinkle1, Twinkle2:std_logic_vector(3 downto 0);
	signal Usual1:std_logic_vector(3 downto 0):="0000";
	signal Usual2:std_logic_vector(3 downto 0):="0000";
	signal mark:std_logic:='0';
	signal status:std_logic_vector(1 downto 0):="00";
begin
	process(clk)begin
		if(clk'event' and clk='1')then
			if(emergent='1')then                
				if(mark='1')then
					mark <='0';
					if(Twinkle1=0 and Twinkle2=0)then 
						if(status="00")then
							Usual1<="0011";
Usual2<="1001";
							status<="01";
					    	elsif(status="01")then
							Usual1<="0000";
							Usual2<="0100";
							status<="10";
						else
							Usual1<="0100";
							Usual2<="0100";
							status<="00";
						end if;
					elsif(tempL=0)then
							Usual1<=Twinkle1-1;
Usual2<="1001";
					else
						Usual1<= Twinkle1;
Usual2<= Usual2-1;
					end if;
				
				elsif(Usual1=0 and Usual2=0)then
					if(status="00")then
						Usual1<="0011";
						Usual2<="1001";
						status<="01";
					elsif(status="01")then
						Usual1<="0000";
						Usual2<="0100";
						status<="10";
					else
						Usual1<="0100";
						Usual2<="0100";
						status<="00";
					end if;
				elsif(Usual2=0)then
					Usual1<= Usual1-1;
					Usual2<= "1001";
				else
					Usual1-1; <= Usual2-1;
				end if;

			elsif(emergent='0')then     
				if(mark='0')then 
					mark<='1';
					Twinkle1<= Usual1;
					Twinkle2<= Usual2;
					Usual1<="0000";
					Usual2<="0000";
				else
					Usual1<=not Usual1;
					Usual2<=not Usual2;
				end if;
			end if;
		end if;
		
	end process;
	Output1<= Usual1;
	Output2<= Usual2;
end one;

3、倒计时显示器模块2

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library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
entity m45_2 is
  port(
       clk:in std_logic;                          
       emergent:in std_logic;                    
       Output12,Output22:out std_logic_vector(3 downto 0)  
  );
end m45_2;

architecture one of m45 is
	signal Twinkle1, Twinkle2:std_logic_vector(3 downto 0);
	signal Usual1:std_logic_vector(3 downto 0):="0000";
	signal Usual2:std_logic_vector(3 downto 0):="0000";
	signal mark:std_logic:='0';
	signal status:std_logic_vector(1 downto 0):="00";
begin
	process(clk)begin
		if(clk'event' and clk='1')then
			if(emergent='1')then                
				if(mark='1')then
					mark <='0';
					if(Twinkle1=0 and Twinkle2=0)then 
						if(status="00")then
							Usual1<="0011";
Usual2<="1001";
							status<="01";
					    	elsif(status="01")then
							Usual1<="0000";
							Usual2<="0100";
							status<="10";
						else
							Usual1<="0100";
							Usual2<="0100";
							status<="00";
						end if;
					elsif(tempL=0)then
							Usual1<=Twinkle1-1;
Usual2<="1001";
					else
						Usual1<= Twinkle1;
Usual2<= Usual2-1;
					end if;
				
				elsif(Usual1=0 and Usual2=0)then
					if(status="00")then
						Usual1<="0011";
						Usual2<="1001";
						status<="01";
					elsif(status="01")then
						Usual1<="0000";
						Usual2<="0100";
						status<="10";
					else
						Usual1<="0100";
						Usual2<="0100";
						status<="00";
					end if;
				elsif(Usual2=0)then
					Usual1<= Usual1-1;
					Usual2<= "1001";
				else
					Usual1-1; <= Usual2-1;
				end if;

			elsif(emergent='0')then     
				if(mark='0')then 
					mark<='1';
					Twinkle1<= Usual1;
					Twinkle2<= Usual2;
					Usual1<="0000";
					Usual2<="0000";
				else
					Usual1<=not Usual1;
					Usual2<=not Usual2;
				end if;
			end if;
		end if;
		
	end process;
	Output12<= Usual1;
	Output22<= Usual2;
end one;

四、结果图像

  1. 电路图

    电路图

  2. 仿真结果

    仿真结果1
    仿真结果2